A memory having a parallel interface such as a DRAM (Dynamic Random Access Memory) is recently being used in various systems. Such system includes a memory access circuit for controlling the access which a processor such as a CPU (Central Processing Unit) performs to a memory.
A typical memory access circuit includes a phase adjusting element for correcting a clock skew. The phase adjusting element is a PLL (phase locked loop) or a DLL (delay locked loop).
The PLL, however, has a large circuit scale and a large power consumption. Therefore, if the clock skew is corrected by using the PLL, the circuit scale and the power consumption of the memory access circuit increase.
Furthermore, the DLL generates a jitter when a signal is propagated through a delay element. This jitter becomes greater as the phase adjustment amount approaches 360 degrees. Therefore, if the clock skew is corrected by using the DLL, a timing margin reduces.